isb
Instruction Synchronization Barrier
ISB {<option>}
Flushes the pipeline and prefetches.
Details
Instruction Synchronization Barrier flushes the instruction pipeline and discards prefetched instructions, ensuring all prior instructions complete before subsequent instructions begin execution. This is a memory ordering operation that does not affect the condition flags. It executes in AArch64 state at EL0 and above.
Pseudocode Operation
Instruction pipeline ← flushed; Prefetched instructions ← discardedExample
ISB
Encoding
Binary Layout
11010101000000110011
CRm
1
10
11111
Operands
-
option
Option (usually 15)
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xD50330DF | ISB {<option>|#<imm>} | A64 | 11010101000000110011 | CRm | 1 | 10 | 11111 |
Description
Instruction Synchronization Barrier flushes the pipeline in the PE and is a context synchronization event. For more information, see Instruction Synchronization Barrier (ISB).
Operation
InstructionSynchronizationBarrier();
if IsFeatureImplemented(FEAT_BRBE) && BRBEBranchOnISB() then
BRBEISB();