sbfx

Signed Bit Field Extract (A32)

SBFX<c> <Rd>, <Rn>, #<lsb>, #<width>

Extracts bits from a register and sign-extends them.

Details

Extracts a bitfield of width bits starting at position lsb from Rn, sign-extends the extracted value, and writes it to Rd. A32 instruction; available in all A32 processor modes. Does not affect PSTATE flags. The condition code suffix controls execution.

Pseudocode Operation

extracted ← Rn<(lsb + width - 1):lsb>; if extracted<(width - 1)> == 1 then Rd ← SignExtend(extracted, width) else Rd ← ZeroExtend(extracted, width);

Example

SBFX r0, r1, #0, #width

Encoding

Binary Layout
cond
01111
0
1
widthm1
Rd
lsb
101
Rn
 
Format Data Proc
Opcode 0x07A00050
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • lsb
    Start Bit
  • width
    Width

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x07A00050 SBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> A32 cond | 01111 | 0 | 1 | widthm1 | Rd | lsb | 101 | Rn
0xF3400000 SBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> T32 11110 | 0 | 11 | 01 | 0 | 0 | Rn | 0 | imm3 | Rd | imm2 | 0 | widthm1

Description

Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    R[d] = SignExtend(R[n]<msbit:lsbit>, 32);