usub16

Unsigned Subtract 16 (A32)

USUB16<c> <Rd>, <Rn>, <Rm>

Parallel sub of two unsigned 16-bit halfwords.

Details

Performs two independent parallel unsigned 16-bit subtractions: the high halfword of Rm is subtracted from the high halfword of Rn, and the low halfword of Rm is subtracted from the low halfword of Rn; results are stored in the corresponding halfwords of Rd. The CPSR GE[3:0] flags are updated to reflect unsigned borrow (no carry-out) in each halfword; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.

Pseudocode Operation

Rd[31:16] ← Rn[31:16] - Rm[31:16]
Rd[15:0] ← Rn[15:0] - Rm[15:0]
GE[3] ← (Rn[31:16] >= Rm[31:16]) ? 1 : 0
GE[2] ← (Rn[31:16] >= Rm[31:16]) ? 0 : 1
GE[1] ← (Rn[15:0] >= Rm[15:0]) ? 1 : 0
GE[0] ← (Rn[15:0] >= Rm[15:0]) ? 0 : 1

Example

USUB16 r0, r1, r2

Encoding

Binary Layout
cond
01100
101
Rn
Rd
1
1
1
1
0
11
1
Rm
 
Format SIMD Integer
Opcode 0x06500F70
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06500F70 USUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01100 | 101 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm
0xFAD0F040 USUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110101 | 101 | Rn | 1111 | Rd | 0 | 1 | 0 | 0 | Rm

Description

Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets PSTATE.GE according to the results of the subtractions.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    diff1 = UInt(R[n]<15:0>) - UInt(R[m]<15:0>);
    diff2 = UInt(R[n]<31:16>) - UInt(R[m]<31:16>);
    R[d]<15:0>  = diff1<15:0>;
    R[d]<31:16> = diff2<15:0>;
    PSTATE.GE<1:0> = if diff1 >= 0 then '11' else '00';
    PSTATE.GE<3:2> = if diff2 >= 0 then '11' else '00';