vmin

Vector Minimum

VMIN<c>.<dt> <Qd>, <Qn>, <Qm>

Selects minimum value from elements.

Pseudocode Operation

for i = 0 to (128 / element_width) - 1:
  Qd[i] ← min(Qn[i], Qm[i])

Example

VMIN.dt q0, q1, q2

Encoding

Binary Layout

1111001

31:25

U

24

0

23

D

22

size

21:20

Vn

19:16

Vd

15:12

0110

11:8

N

7

0

6

M

5

1

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF2000610

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qn
  First source 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2200F00	VMIN{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		A32		1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1111 | N | 0 | M | 0 | Vm
0xF2200F40	VMIN{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		A32		1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1111 | N | 1 | M | 0 | Vm
0xEF200F00	VMIN{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		T32		111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1111 | N | 0 | M | 0 | Vm
0xEF200F40	VMIN{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		T32		111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1111 | N | 1 | M | 0 | Vm
0xF2000610	VMIN{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		A32		1111001 | U | 0 | D | size | Vn | Vd | 0110 | N | 0 | M | 1 | Vm
0xF2000650	VMIN{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		A32		1111001 | U | 0 | D | size | Vn | Vd | 0110 | N | 1 | M | 1 | Vm
0xEF000610	VMIN{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		T32		111 | U | 11110 | D | size | Vn | Vd | 0110 | N | 0 | M | 1 | Vm
0xEF000650	VMIN{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		T32		111 | U | 11110 | D | size | Vn | Vd | 0110 | N | 1 | M | 1 | Vm

Description

Vector Minimum compares corresponding elements in two vectors, and copies the smaller of each pair into the corresponding element in the destination vector. The operand vector elements can be any one of: The result vector elements are the same size as the operand vector elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Int(Elem[D[n+r],e,esize], unsigned);
            op2 = Int(Elem[D[m+r],e,esize], unsigned);
            result = if maximum then Max(op1,op2) else Min(op1,op2);
            Elem[D[d+r],e,esize] = result<esize-1:0>;