vorn

Vector OR NOT

VORN<c> <Qd>, <Qn>, <Qm>

Bitwise OR with NOT (Vd = Vn | ~Vm).

Details

Performs bitwise OR of the first operand with the bitwise NOT of the second operand (Qd = Qn | ~Qm), element-wise. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.

Pseudocode Operation

for i = 0 to 127
  Qd[i] ← Qn[i] | ~Qm[i]

Example

VORN q0, q1, q2

Encoding

Binary Layout
1111001
0
0
D
11
Vn
Vd
0001
N
1
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2300150
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2300110 VORN{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm> A32 1111001 | 0 | 0 | D | 11 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF2300150 VORN{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm> A32 1111001 | 0 | 0 | D | 11 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xEF300110 VORN{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm> T32 111 | 0 | 11110 | D | 11 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xEF300150 VORN{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm> T32 111 | 0 | 11110 | D | 11 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xF2800110 VORN{<c>}{<q>}.I16 {<Dd>,} <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4
0xF2800150 VORN{<c>}{<q>}.I16 {<Qd>,} <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 0 | 1 | imm4
0xF2800910 VORN{<c>}{<q>}.I32 {<Dd>,} <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4
0xF2800950 VORN{<c>}{<q>}.I32 {<Qd>,} <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 0 | 1 | imm4
0xEF800110 VORN{<c>}{<q>}.I16 {<Dd>,} <Dd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4
0xEF800150 VORN{<c>}{<q>}.I16 {<Qd>,} <Qd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 0 | 1 | imm4
0xEF800910 VORN{<c>}{<q>}.I32 {<Dd>,} <Dd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4
0xEF800950 VORN{<c>}{<q>}.I32 {<Qd>,} <Qd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 0 | 1 | imm4

Description

Vector bitwise OR NOT (register) performs a bitwise OR NOT operation between two registers, and places the result in the destination register. The operand and result registers can be quadword or doubleword. They must all be the same size. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        D[d+r] = D[n+r] OR NOT(D[m+r]);