ret

Return from Subroutine

RET {<Xn>}

Branches to address in LR (or specified register).

Pseudocode Operation

if Xn is not specified then
  target ← X30
else
  target ← Xn
PC ← target

Example

RET

Encoding

Binary Layout

1101011

31:25

22:21

11111

20:16

0000

15:12

9:5

00000

4:0

Format Branch

Opcode 0xD65F0000

Extension Base

Operands

Xn
Addr (Def: X30)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xD65F0000	RET {<Xn>}		A64		1101011 \| 0 \| 0 \| 10 \| 11111 \| 0000 \| 0 \| 0 \| Rn \| 00000

Description

Return from subroutine branches unconditionally to an address in a register, with a hint that this is a subroutine return.

Operation

bits(64) target = X[n, 64];

if (IsFeatureImplemented(FEAT_GCS) && GCSPCREnabled(PSTATE.EL)) then
    target = LoadCheckGCSRecord(target, GCSInstType_PRET);
    SetCurrentGCSPointer(GetCurrentGCSPointer() + 8);

// Value in BTypeNext will be used to set PSTATE.BTYPE
BTypeNext = '00';

BranchTo(target, BranchType_RET, FALSE);

ret