vrev32

Vector Reverse 32

VREV32<c>.<dt> <Qd>, <Qm>

Reverses elements within 32-bit words.

Details

Reverses the byte or halfword order within each 32-bit word element in the source register, depending on element size. For 8-bit elements, reverses bytes within words; for 16-bit elements, reverses halfwords within words. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; operates on integer data types.

Pseudocode Operation

if element_size == 8:
  for i = 0 to 127 by 32:
    for j = 0 to 31 by 8:
      Qd[i+j+7:i+j] ← Qm[i+31-j:i+24-j]
else if element_size == 16:
  for i = 0 to 127 by 32:
    Qd[i+31:i+16] ← Qm[i+15:i+0]
    Qd[i+15:i+0] ← Qm[i+31:i+16]

Example

VREV32.dt q0, q2

Encoding

Binary Layout
111100111
D
11
size
00
Vd
0
00
01
0
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xF3B00080
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B00080 VREV32{<c>}{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 01 | 0 | M | 0 | Vm
0xF3B000C0 VREV32{<c>}{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 00 | Vd | 0 | 00 | 01 | 1 | M | 0 | Vm
0xFFB00080 VREV32{<c>}{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 00 | Vd | 0 | 00 | 01 | 0 | M | 0 | Vm
0xFFB000C0 VREV32{<c>}{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 00 | Vd | 0 | 00 | 01 | 1 | M | 0 | Vm

Description

Vector Reverse in words reverses the order of 8-bit or 16-bit elements in each word of the vector, and places the result in the corresponding destination vector. There is no distinction between data types, other than size. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();

    bits(64) result;
    integer element;
    integer rev_element;
    for r = 0 to regs-1
        element = 0;
        for c = 0 to containers-1
            rev_element = (element + elements_per_container) - 1;
            for e = 0 to elements_per_container-1
                Elem[result, rev_element, esize] = Elem[D[m+r], element, esize];
                element = element + 1;
                rev_element = rev_element - 1;
        D[d+r] = result;