fmax
Vector Floating-Point Maximum
FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
Compares and returns the larger value per element.
Details
Compares corresponding floating-point elements in two NEON vectors and places the larger value in the destination vector for each element. No NEON flag bits are affected; this is a per-element maximum operation available in 32-bit and 64-bit floating-point forms (controlled by sz). Executes on AArch64 with NEON/ASIMD extension; the Q bit selects between 64-bit (Q=0) and 128-bit (Q=1) vector width.
Pseudocode Operation
for i = 0 to elements_in_vector-1:
element_size = 32 if sz==0 else 64
Vd[element][element_size-1:0] = max_fp(Vn[element][element_size-1:0], Vm[element][element_size-1:0])Example
FMAX v0.4s.T, v1.4s.T, v2.4s.T
Encoding
Binary Layout
0
Q
0
01110
0
sz
1
Rm
11110
1
Rn
Rd
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E403400 | FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | 0 | 10 | Rm | 00 | 110 | 1 | Rn | Rd | ||
| 0x0E20F400 | FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | 0 | sz | 1 | Rm | 11110 | 1 | Rn | Rd | ||
| 0x1EE04800 | FMAX <Hd>, <Hn>, <Hm> | A64 | 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 01 | 00 | 10 | Rn | Rd | ||
| 0x1E204800 | FMAX <Sd>, <Sn>, <Sm> | A64 | 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 01 | 00 | 10 | Rn | Rd | ||
| 0x1E604800 | FMAX <Dd>, <Dn>, <Dm> | A64 | 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 01 | 00 | 10 | Rn | Rd | ||
| 0xC120A100 | FMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101000 | 0100 | 0 | Zdn | 0 | ||
| 0xC120A900 | FMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101010 | 0100 | 0 | Zdn | 0 | 0 | ||
| 0xC120B100 | FMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } | A64 | 11000001 | size | 1 | Zm | 0101100 | 010 | 0 | 0 | Zdn | 0 | ||
| 0xC120B900 | FMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } | A64 | 11000001 | size | 1 | Zm | 00101110 | 010 | 0 | 0 | Zdn | 0 | 0 | ||
| 0x651E8000 | FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> | A64 | 01100101 | size | 011 | 11 | 0 | 100 | Pg | 0000 | i1 | Zdn | ||
| 0x65068000 | FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 01100101 | size | 00 | 011 | 0 | 100 | Pg | Zm | Zdn |
Description
Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
When FPCR.AH is 0, the behavior is as follows:
When FPCR.AH is 1, the behavior is as follows:
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;
for e = 0 to elements-1
if pair then
element1 = Elem[concat, 2*e, esize];
element2 = Elem[concat, (2*e)+1, esize];
else
element1 = Elem[operand1, e, esize];
element2 = Elem[operand2, e, esize];
if minimum then
Elem[result, e, esize] = FPMin(element1, element2, FPCR);
else
Elem[result, e, esize] = FPMax(element1, element2, FPCR);
V[d, datasize] = result;