fadd
Vector Floating-Point Add
FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
Adds elements of two floating-point vectors.
Details
Adds corresponding floating-point elements in Vn and Vm, storing results in Vd. Supports both 32-bit (sz=0) and 64-bit (sz=1) floating-point lanes across 64-bit (Q=0) or 128-bit (Q=1) vectors. Floating-point exception behavior follows IEEE 754 semantics; no integer condition flags are affected. Executes in AArch64 state with NEON extension.
Pseudocode Operation
if sz == '0' then
for i = 0 to (datasize / 32) - 1
Vd[i*32 +: 32] ← FPAdd(Vn[i*32 +: 32], Vm[i*32 +: 32], FPCR)
else
for i = 0 to (datasize / 64) - 1
Vd[i*64 +: 64] ← FPAdd(Vn[i*64 +: 64], Vm[i*64 +: 64], FPCR)Example
FADD v0.4s.T, v1.4s.T, v2.4s.T
Encoding
Binary Layout
0
Q
0
011100
sz
1
Rm
11010
1
Rn
Rd
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E401400 | FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | 0 | 10 | Rm | 00 | 010 | 1 | Rn | Rd | ||
| 0x0E20D400 | FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 011100 | sz | 1 | Rm | 11010 | 1 | Rn | Rd | ||
| 0x1EE02800 | FADD <Hd>, <Hn>, <Hm> | A64 | 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 001 | 0 | 10 | Rn | Rd | ||
| 0x1E202800 | FADD <Sd>, <Sn>, <Sm> | A64 | 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 0 | 10 | Rn | Rd | ||
| 0x1E602800 | FADD <Dd>, <Dn>, <Dm> | A64 | 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 0 | 10 | Rn | Rd | ||
| 0x65188000 | FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> | A64 | 01100101 | size | 011 | 00 | 0 | 100 | Pg | 0000 | i1 | Zdn | ||
| 0x65008000 | FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 01100101 | size | 00 | 000 | 0 | 100 | Pg | Zm | Zdn | ||
| 0x65000000 | FADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | A64 | 01100101 | size | 0 | Zm | 000 | 00 | 0 | Zn | Zd | ||
| 0xC1A01C00 | FADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } | A64 | 110000011 | sz | 1000000 | Rv | 111 | Zm | 00 | 0 | off3 | ||
| 0xC1A41C00 | FADD ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } | A64 | 110000011 | 0 | 1001000 | Rv | 111 | Zm | 00 | 0 | off3 | ||
| 0xC1A11C00 | FADD ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } | A64 | 110000011 | sz | 1000010 | Rv | 111 | Zm | 000 | 0 | off3 | ||
| 0xC1A51C00 | FADD ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } | A64 | 110000011 | 0 | 1001010 | Rv | 111 | Zm | 000 | 0 | off3 |
Description
Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;
for e = 0 to elements-1
if pair then
element1 = Elem[concat, 2*e, esize];
element2 = Elem[concat, (2*e)+1, esize];
else
element1 = Elem[operand1, e, esize];
element2 = Elem[operand2, e, esize];
Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
V[d, datasize] = result;