sshr

Vector Signed Shift Right

SSHR <Vd>.<T>, <Vn>.<T>, #<shift>

Shifts elements right (arithmetic/sign-extending).

Details

The Vector Signed Shift Right instruction shifts elements right (arithmetic/sign-extending).

Pseudocode Operation

// Shifts elements right (arithmetic/sign-extending)

Example

SSHR v0.4s.T, v1.4s.T, #LSL

Encoding

Binary Layout
0
Q
001111
0
imm
0000
01
Rn
Rd
 
Format SIMD Shift Imm
Opcode 0x0F000400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • shift
    Imm