sshr

Vector Signed Shift Right

SSHR <Vd>.<T>, <Vn>.<T>, #<shift>

Shifts elements right (arithmetic/sign-extending).

Details

Shifts each signed element in the vector right by an immediate shift count, filling the vacated bits with the sign bit (arithmetic right shift). The shift amount is encoded in the imm field; the element size is determined by the type specifier (.8B, .4H, .2S, .1D, etc.). Condition flags are not affected. This is a NEON instruction available in AArch64 execution state.

Pseudocode Operation

shift_amount ← imm
for i = 0 to elements_in_vector - 1
  Vd[i] ← SignExtend(Vn[i] >> shift_amount, element_width)

Example

SSHR v0.4s.T, v1.4s.T, #LSL

Encoding

Binary Layout
0
Q
0
011110
immh
immb
00
0
0
01
Rn
Rd
 
Format SIMD Shift Imm
Opcode 0x0F000400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • shift
    Imm

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F400400 SSHR D<d>, D<n>, #<shift> A64 01 | 0 | 111110 | immh | immb | 00 | 0 | 0 | 01 | Rn | Rd
0x0F000400 SSHR <Vd>.<T>, <Vn>.<T>, #<shift> A64 0 | Q | 0 | 011110 | immh | immb | 00 | 0 | 0 | 01 | Rn | Rd

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) operand2;
bits(datasize) result;
integer element;

operand2 = if accumulate then V[d, datasize] else Zeros(datasize);
for e = 0 to elements-1
    element = RShr(Int(Elem[operand, e, esize], unsigned), shift, round);
    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

V[d, datasize] = result;