vclz

Vector Count Leading Zeros

VCLZ<c>.<dt> <Qd>, <Qm>

Counts number of consecutive zeros.

Pseudocode Operation

for i = 0 to (128 / element_size) - 1 do
  count ← 0
  for j = element_size - 1 downto 0 do
    if (Qm[i] >> j) & 1 == 0 then
      count ← count + 1
    else
      break
    end if
  end for
  Qd[i] ← count
end for

Example

VCLZ.dt q0, q2

Encoding

Binary Layout
111100111
31:23
D
22
11
21:20
size
19:18
00
17:16
Vd
15:12
0
11
1001
10:7
1
6
M
5
0
4
Vm
3:0
 
Format NEON 2-Reg
Opcode 0xF3B004C0
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B00480 VCLZ{<c>}{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 00 | Vd | 0 | 1001 | 0 | M | 0 | Vm
0xF3B004C0 VCLZ{<c>}{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 00 | Vd | 0 | 1001 | 1 | M | 0 | Vm
0xFFB00480 VCLZ{<c>}{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 00 | Vd | 0 | 1001 | 0 | M | 0 | Vm
0xFFB004C0 VCLZ{<c>}{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 00 | Vd | 0 | 1001 | 1 | M | 0 | Vm

Description

Vector Count Leading Zeros counts the number of consecutive zeros, starting from the most significant bit, in each element in a vector, and places the results in a second vector. The operand vector elements can be any one of 8-bit, 16-bit, or 32-bit integers. There is no distinction between signed and unsigned integers. The result vector elements are the same data type as the operand vector elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            Elem[D[d+r],e,esize] = CountLeadingZeroBits(Elem[D[m+r],e,esize])<esize-1:0>;