add

Add (A32)

ADD{S}<c> <Rd>, <Rn>, <Rm> {, <shift>}

Adds two 32-bit values.

Details

Adds two 32-bit operands and stores the result in the destination register. If the S bit is set, the condition flags (N, Z, C, V) are updated based on the result; otherwise they are unaffected. This is an A32 instruction where the condition code (cond) field determines execution based on the current condition flags.

Pseudocode Operation

result ← Rn + (Rm << shift_amount)
Rd ← result[31:0]
if S then
  N ← result[31]
  Z ← (result == 0)
  C ← CarryOut(Rn, Rm << shift_amount)
  V ← OverflowFrom(Rn, Rm << shift_amount)

Example

ADD r0, r1, r2

Encoding

Binary Layout
cond
0000
100
0
Rn
Rd
imm5
stype
0
Rm
 
Format Data Proc
Opcode 0x00800000
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x028F0000 ADD{<c>}{<q>} <Rd>, PC, #<const> A32 cond | 0010 | 100 | 0 | 1111 | Rd | imm12
0xA000 ADD{<c>}{<q>} <Rd>, PC, #<imm8> T32 1010 | 0 | Rd | imm8
0xF20F0000 ADDW{<c>}{<q>} <Rd>, PC, #<imm12> T32 11110 | i | 10 | 0 | 0 | 0 | 0 | 1111 | 0 | imm3 | Rd | imm8
0x02800000 ADD{<c>}{<q>} {<Rd>,} <Rn>, #<const> A32 cond | 0010 | 100 | 0 | Rn | Rd | imm12
0x1C00 ADD<c>{<q>} <Rd>, <Rn>, #<imm3> T32 000111 | 0 | imm3 | Rn | Rd
0x3000 ADD<c>{<q>} <Rdn>, #<imm8> T32 001 | 10 | Rdn | imm8
0xF1000000 ADD<c>.W {<Rd>,} <Rn>, #<const> T32 11110 | i | 0 | 1000 | 0 | Rn | 0 | imm3 | Rd | imm8
0x00800060 ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX A32 cond | 0000 | 100 | 0 | Rn | Rd | 00000 | 11 | 0 | Rm
0x00800000 ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} A32 cond | 0000 | 100 | 0 | Rn | Rd | imm5 | stype | 0 | Rm
0x1800 ADD<c>{<q>} <Rd>, <Rn>, <Rm> T32 000110 | 0 | Rm | Rn | Rd
0x4400 ADD<c>{<q>} <Rdn>, <Rm> T32 010001 | 00 | DN | Rm | Rdn
0xEB000030 ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX T32 1110101 | 1000 | 0 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEB000000 ADD<c>.W {<Rd>,} <Rn>, <Rm> T32 1110101 | 1000 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm
0x00800010 ADD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> A32 cond | 0000 | 100 | 0 | Rn | Rd | Rs | 0 | stype | 1 | Rm

Description

Add (register) adds a register value and an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    shifted = Shift(R[m], shift_t, shift_n, PSTATE.C);
    (result, nzcv) = AddWithCarry(R[n], shifted, '0');
    if d == 15 then
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;