compact

SVE Compact Vector

COMPACT <Zd>.<T>, <Pg>, <Zn>.<T>

Packs active elements to the bottom of the vector.

Pseudocode Operation

integer esize = 8 << UInt(sz);
integer elements = VL / esize;
integer dst_index = 0;
for e = 0 to elements-1
  if Pg[e] == '1' then
    Zd[dst_index * esize +: esize] = Zn[e * esize +: esize];
    dst_index = dst_index + 1;
for e = dst_index to elements-1
  Zd[e * esize +: esize] = 0;

Example

COMPACT z0.s.T, p0/m, z1.s.T

Encoding

Binary Layout

00000101

31:24

size

23:22

100001100

21:13

12:10

9:5

4:0

Format SVE Permute

Opcode 0x05218000

Extension SVE

Operands

Zd
Destination scalable vector register (SVE)
Pg
Mask
Zn
First source scalable vector register (SVE)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x05218000	COMPACT <Zd>.<T>, <Pg>, <Zn>.<T>		A64		00000101 \| size \| 100001100 \| Pg \| Zn \| Zd

Description

Read the active elements from the source vector and pack them into the lowest-numbered elements of the destination vector. Then set any remaining elements of the destination vector to zero. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Zeros(VL);
integer x = 0;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand1, e, esize];
        Elem[result, x, esize] = element;
        x = x + 1;

Z[d, VL] = result;