fnmul

Floating-Point Negated Multiply (Scalar)

FNMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>

Calculates -(Vn * Vm).

Pseudocode Operation

if type == 0:
  Vd ← -(Vn_float16 × Vm_float16)
else if type == 1:
  Vd ← -(Vn_float32 × Vm_float32)
else if type == 2:
  Vd ← -(Vn_float64 × Vm_float64)

Example

FNMUL Dd, Dn, Dm

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
Rm
20:16
1
15
00010
14:10
Rn
9:5
Rd
4:0
 
Format FP Data Processing
Opcode 0x1E208800
Extension Floating Point

Operands

  • Hd|Sd|Dd
    Destination SIMD&FP register (half, single or double-precision)
  • Hn|Sn|Dn
    First source SIMD&FP register (half, single or double-precision)
  • Hm|Sm|Dm
    Second source SIMD&FP register (half, single or double-precision)

Related

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1EE08800 FNMUL <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 1 | 00010 | Rn | Rd
0x1E208800 FNMUL <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 1 | 00010 | Rn | Rd
0x1E608800 FNMUL <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 1 | 00010 | Rn | Rd

Description

Floating-point Multiply-Negate (scalar). This instruction multiplies the floating-point values of the two source SIMD&FP registers, and writes the negation of the result to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);

bits(esize) product = FPMul(operand1, operand2, FPCR);
product = FPNeg(product, FPCR);
Elem[result, 0, esize] = product;

V[d, 128] = result;