ldar

Load-Acquire Register

LDAR <Wt>, [<Xn|SP>]

Loads a word with Acquire semantics.

Pseudocode Operation

Wt ← ZeroExtend(Mem32[Xn], 32)
# Acquire semantics: subsequent memory operations appear after this load

Example

LDAR w3, [x1]

Encoding

Binary Layout

10

31:30

0010001

29:23

1

22

0

21

11111

20:16

1

15

11111

14:10

Rn

9:5

Rt

4:0

 

Format Load/Store

Opcode 0x88DFFC00

Extension Base (Atomic)

Operands

• Wt
  Transfer 32-bit integer register (load/store)
• Xn
  First source / base 64-bit integer register

Related

Across architectures

Load-Acquire : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base (Atomic)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x88DFFC00	LDAR <Wt>, [<Xn|SP>{, #0}]		A64		10 | 0010001 | 1 | 0 | 11111 | 1 | 11111 | Rn | Rt
0xC8DFFC00	LDAR <Xt>, [<Xn|SP>{, #0}]		A64		11 | 0010001 | 1 | 0 | 11111 | 1 | 11111 | Rn | Rt

Description

Load-Acquire Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(elsize) data;
constant integer dbytes = elsize DIV 8;

AccessDescriptor accdesc;
accdesc = CreateAccDescAcqRel(MemOp_LOAD, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

data = Mem[address, dbytes, accdesc];
X[t, regsize] = ZeroExtend(data, regsize);