vand

Vector Bitwise AND

VAND<c> <Qd>, <Qn>, <Qm>

Bitwise AND of two vectors.

Details

Performs bitwise AND on corresponding bits of two 128-bit NEON registers and stores the result in the destination register. This instruction is data-type agnostic and operates on the bit patterns directly. No flags are affected.

Pseudocode Operation

Qd ← Qn AND Qm

Example

VAND q0, q1, q2

Encoding

Binary Layout
1111001
0
0
D
00
Vn
Vd
0001
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000110
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000110 VAND{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm> A32 1111001 | 0 | 0 | D | 00 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF2000150 VAND{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm> A32 1111001 | 0 | 0 | D | 00 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xEF000110 VAND{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm> T32 111 | 0 | 11110 | D | 00 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xEF000150 VAND{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm> T32 111 | 0 | 11110 | D | 00 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xF2800130 VAND{<c>}{<q>}.I16 {<Dd>,} <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 1 | 1 | imm4
0xF2800170 VAND{<c>}{<q>}.I16 {<Qd>,} <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 1 | 1 | imm4
0xF2800930 VAND{<c>}{<q>}.I32 {<Dd>,} <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 1 | 1 | imm4
0xF2800970 VAND{<c>}{<q>}.I32 {<Qd>,} <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 1 | 1 | imm4
0xEF800130 VAND{<c>}{<q>}.I16 {<Dd>,} <Dd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 1 | 1 | imm4
0xEF800170 VAND{<c>}{<q>}.I16 {<Qd>,} <Qd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 1 | 1 | imm4
0xEF800930 VAND{<c>}{<q>}.I32 {<Dd>,} <Dd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 1 | 1 | imm4
0xEF800970 VAND{<c>}{<q>}.I32 {<Qd>,} <Qd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 1 | 1 | imm4

Description

Vector Bitwise AND (register) performs a bitwise AND operation between two registers, and places the result in the destination register. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        D[d+r] = D[n+r] AND D[m+r];