fdiv

Floating-Point Divide (Half-Precision)

FDIV <Vd>.8H, <Vn>.8H, <Vm>.8H

Divides two half-precision floating-point vectors.

Pseudocode Operation

for i = 0 to 7
  Vd[i*16 +: 16] ← FP16_Div(Vn[i*16 +: 16], Vm[i*16 +: 16])

Example

FDIV v0.4s.8H, v1.4s.8H, v2.4s.8H

Encoding

Binary Layout
0
31
Q
30
1
29
01110
28:24
0
23
10
22:21
Rm
20:16
00
15:14
111
13:11
1
10
Rn
9:5
Rd
4:0
 
Format NEON FP16
Opcode 0x2E403C00
Extension FEAT_FP16 (NEON)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Related

Other forms of fdiv

  • fdiv Floating-Point Divide (Scalar)
  • fdiv Vector Floating-Point Divide
  • fdiv SVE Floating-Point Divide
  • fdiv Floating-point Divide (Single)
  • fdiv Floating-point Divide (Double)

More in FEAT_FP16 (NEON)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E403C00 FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 111 | 1 | Rn | Rd
0x2E20FC00 FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11111 | 1 | Rn | Rd
0x1EE01800 FDIV <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 0001 | 10 | Rn | Rd
0x1E201800 FDIV <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0001 | 10 | Rn | Rd
0x1E601800 FDIV <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0001 | 10 | Rn | Rd
0x650D8000 FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 110 | 1 | 100 | Pg | Zm | Zdn

Description

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);

V[d, datasize] = result;