fmul

SVE Floating-Point Multiply

FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Multiplies floating-point elements under predicate.

Details

Multiplies corresponding floating-point elements in Zdn and Zm, writing results back to Zdn under the control of predicate Pg in merging mode. The operation is performed element-by-element on 32-bit, 64-bit, or 16-bit (half-precision) floating-point values as indicated by the type specifier. No condition flags are affected; inactive elements are preserved in Zdn. AArch64-only instruction requiring SVE extension.

Pseudocode Operation

for i ← 0 to VL/esize - 1
  if Pg[i] == 1 then
    Zdn[i] ← Zdn[i] * Zm[i]
  else
    Zdn[i] ← Zdn[i]  // unchanged

Example

FMUL z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
01100101
size
00
001
0
100
Pg
Zm
Zdn
 
Format SVE FP Binary
Opcode 0x65028000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F009000 FMUL <Hd>, <Hn>, <Vm>.H[<index>] A64 01 | 0 | 11111 | 00 | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x5F809000 FMUL <V><d>, <V><n>, <Vm>.<Ts>[<index>] A64 01 | 0 | 111111 | sz | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x0F009000 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>] A64 0 | Q | 0 | 01111 | 00 | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x0F809000 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] A64 0 | Q | 0 | 011111 | sz | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x2E401C00 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 011 | 1 | Rn | Rd
0x2E20DC00 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11011 | 1 | Rn | Rd
0x1EE00800 FMUL <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 0 | 00010 | Rn | Rd
0x1E200800 FMUL <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0 | 00010 | Rn | Rd
0x1E600800 FMUL <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0 | 00010 | Rn | Rd
0x651A8000 FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 01 | 0 | 100 | Pg | 0000 | i1 | Zdn
0x65028000 FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 001 | 0 | 100 | Pg | Zm | Zdn
0x65000800 FMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 01 | 0 | Zn | Zd
0x64202000 FMUL <Zd>.H, <Zn>.H, <Zm>.H[<imm>] A64 01100100 | 0 | i3h | 1 | i3l | Zm | 0010 | 0 | 0 | Zn | Zd
0x64A02000 FMUL <Zd>.S, <Zn>.S, <Zm>.S[<imm>] A64 01100100 | 1 | 0 | 1 | i2 | Zm | 0010 | 0 | 0 | Zn | Zd

Description

Multiply active floating-point elements of the first source vector by corresponding floating-point elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    bits(esize) element1 = Elem[operand1, e, esize];
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element2 = Elem[operand2, e, esize];
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
    else
        Elem[result, e, esize] = element1;

Z[dn, VL] = result;