ubfm

Unsigned Bitfield Move

UBFM <Wd>, <Wn>, #<immr>, #<imms>

Extracts/Inserts bitfield (Zero Extend).

Details

Extracts a bitfield from Wn (or Xn in 64-bit variant) and zero-extends it into Wd (or Xd). The bitfield is selected by rotating right by immr positions and then masking imms bits. No arithmetic flags are affected. This is AArch64-only and commonly used for zero-extension of bit ranges.

Pseudocode Operation

width ← size; elem ← (Wn >> immr) | (Wn << (width - immr)); mask ← (1 << (imms + 1)) - 1; Wd ← elem & mask; Wd[63:32] ← 0

Example

UBFM w0, w1, #immr, #imms

Encoding

Binary Layout
0
10
100110
0
immr
imms
Rn
Rd
 
Format Bitfield
Opcode 0x53000000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • immr
    Rotate
  • imms
    Size

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x53000000 UBFM <Wd>, <Wn>, #<immr>, #<imms> A64 0 | 10 | 100110 | 0 | immr | imms | Rn | Rd
0xD3400000 UBFM <Xd>, <Xn>, #<immr>, #<imms> A64 1 | 10 | 100110 | 1 | immr | imms | Rn | Rd

Description

Unsigned Bitfield Move is usually accessed via one of its aliases, which are always preferred for disassembly. If <imms> is greater than or equal to <immr>, this copies a bitfield of (<imms>-<immr>+1) bits starting from bit position <immr> in the source register to the least significant bits of the destination register. If <imms> is less than <immr>, this copies a bitfield of (<imms>+1) bits from the least significant bits of the source register to bit position (regsize-<immr>) of the destination register, where regsize is the destination register size of 32 or 64 bits. In both cases the destination bits below and above the bitfield are set to zero.

Operation

bits(datasize) src = X[n, datasize];

// perform bitfield move on low bits
bits(datasize) bot = ROR(src, r) AND wmask;


// combine extension bits and result bits
X[d, datasize] = bot AND tmask;