st1b

SVE Store Contiguous Bytes

ST1B { <Zt>.B }, <Pg>, [<Xn|SP>]

Stores active bytes from vector to memory.

Details

Stores active bytes from a SVE vector register to memory under predicate control. Only elements where the corresponding predicate bit is set are written; inactive elements do not generate memory operations. No flags are affected.

Pseudocode Operation

for i = 0 to VL/8-1
  if Pg[i] == 1 then
    [Xn + i] ← Zt.B[i]

Example

ST1B p0/m, [x1]

Encoding

Binary Layout
1110010
00
size
Rm
010
Pg
Rn
Zt
 
Format SVE Store
Opcode 0xE4004000
Extension SVE

Operands

  • Zt
    Src Vector
  • Pg
    Predicate
  • Xn
    Base Addr

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xA0600000 ST1B { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000110 | imm4 | 0 | 0 | 0 | PNg | Rn | Zt | 0
0xA0608000 ST1B { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000110 | imm4 | 1 | 0 | 0 | PNg | Rn | Zt | 0 | 0
0xA0200000 ST1B { <Zt1>.B-<Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>] A64 10100000001 | Rm | 0 | 0 | 0 | PNg | Rn | Zt | 0
0xA0208000 ST1B { <Zt1>.B-<Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>] A64 10100000001 | Rm | 1 | 0 | 0 | PNg | Rn | Zt | 0 | 0
0xA1600000 ST1B { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010110 | imm4 | 0 | 0 | 0 | PNg | Rn | T | 0 | Zt
0xA1608000 ST1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010110 | imm4 | 1 | 0 | 0 | PNg | Rn | T | 0 | 0 | Zt
0xA1200000 ST1B { <Zt1>.B, <Zt2>.B }, <PNg>, [<Xn|SP>, <Xm>] A64 10100001001 | Rm | 0 | 0 | 0 | PNg | Rn | T | 0 | Zt
0xA1208000 ST1B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <PNg>, [<Xn|SP>, <Xm>] A64 10100001001 | Rm | 1 | 0 | 0 | PNg | Rn | T | 0 | 0 | Zt
0xE460A000 ST1B { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}] A64 1110010 | 0 | 0 | 11 | imm5 | 101 | Pg | Zn | Zt
0xE440A000 ST1B { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}] A64 1110010 | 0 | 0 | 10 | imm5 | 101 | Pg | Zn | Zt
0xE400E000 ST1B { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 1110010 | 0 | 0 | size | 0 | imm4 | 111 | Pg | Rn | Zt
0xE4004000 ST1B { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>] A64 1110010 | 00 | size | Rm | 010 | Pg | Rn | Zt
0xE4008000 ST1B { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] A64 1110010 | 0 | 0 | 00 | Zm | 1 | xs | 0 | Pg | Rn | Zt
0xE4408000 ST1B { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] A64 1110010 | 0 | 0 | 10 | Zm | 1 | xs | 0 | Pg | Rn | Zt

Description

Contiguous store of bytes from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(64) offset;
bits(VL) src;
constant integer mbytes = msize DIV 8;
boolean contiguous = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = TRUE;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];
    offset = X[m, 64];
    src = Z[t, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer eoff = UInt(offset) + e;
        bits(64) addr = GenerateAddress(base, eoff * mbytes, accdesc);
        Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;