smlawt
Signed Multiply Accumulate (Word x Top)
Performs SMULWT and adds to accumulator.
Pseudocode Operation
product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[31:16], 48);
temp ← product[47:16];
result ← temp + Ra;
if OverflowFrom_Addition(temp, Ra) then Q ← 1; end if;
Rd ← result;Example
Encoding
Operands
-
Rd
Destination general-purpose register -
Rn
Word -
Rm
Half -
Ra
Acc
Related
More in A32 (DSP)
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x012000C0 | SMLAWT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> | A32 | cond | 00010 | 01 | 0 | Rd | Ra | Rm | 1 | 1 | 0 | 0 | Rn | ||
| 0xFB300010 | SMLAWT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> | T32 | 111110110 | 011 | Rn | Ra | Rd | 00 | 0 | 1 | Rm |
Description
Signed Multiply Accumulate (word by halfword) performs a signed multiply accumulate operation. The multiply acts on a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are added to a 32-bit accumulate value and the result is written to the destination register. The bottom 16 bits of the 48-bit product are ignored. If overflow occurs during the addition of the accumulate value, the instruction sets PSTATE.Q to 1. No overflow can occur during the multiplication.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
result = SInt(R[n]) * SInt(operand2) + (SInt(R[a]) << 16);
R[d] = result<47:16>;
if (result >> 16) != SInt(R[d]) then // Signed overflow
PSTATE.Q = '1';