smultt
Signed Multiply (Top x Top)
SMULTT<c> <Rd>, <Rn>, <Rm>
Multiplies top 16 bits of Rn and top 16 bits of Rm.
Details
A32 DSP multiply instruction that multiplies the top 16 bits (signed) of Rn by the top 16 bits (signed) of Rm and stores the 32-bit result in Rd. The instruction is conditional and does not affect the NZCV condition flags. Q flag behavior is not documented for this instruction in standard architectures.
Pseudocode Operation
operand1 = SignExtend(Rn<31:16>, 32)
operand2 = SignExtend(Rm<31:16>, 32)
Rd = (operand1 * operand2)<31:0>Example
SMULTT r0, r1, r2
Encoding
Binary Layout
cond
00010
11
0
Rd
0000
Rm
1
1
1
0
Rn
Operands
-
Rd
Destination general-purpose register -
Rn
Src 1 (Top) -
Rm
Src 2 (Top)
Reference (Arm AArch32 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x016000E0 | SMULTT{<c>}{<q>} {<Rd>,} <Rn>, <Rm> | A32 | cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 1 | 1 | 0 | Rn | ||
| 0xFB10F030 | SMULTT{<c>}{<q>} {<Rd>,} <Rn>, <Rm> | T32 | 111110110 | 001 | Rn | 1111 | Rd | 00 | 1 | 1 | Rm |
Description
Signed Multiply (halfwords) multiplies two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is written to the destination register. No overflow is possible during this instruction.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
operand1 = if n_high then R[n]<31:16> else R[n]<15:0>;
operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
result = SInt(operand1) * SInt(operand2);
R[d] = result<31:0>;
// Signed overflow cannot occur