vrsqrts

Vector Reciprocal Square Root Step

VRSQRTS<c>.F32 <Qd>, <Qn>, <Qm>

Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2.

Details

The Vector Reciprocal Square Root Step instruction newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2.

Pseudocode Operation

// Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2

Example

VRSQRTS.F32 q0, q1, q2

Encoding

Binary Layout
11110010
0
0
1
Vn
Vd
1111
N
Q
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2200F10
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register