vrsqrts

Vector Reciprocal Square Root Step

VRSQRTS<c>.F32 <Qd>, <Qn>, <Qm>

Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2.

Details

Vector Reciprocal Square Root Step performs a Newton-Raphson step for reciprocal square root refinement on 32-bit floating-point SIMD elements: Qd = (3.0 - (Qn * Qm)) / 2.0. This operation is typically used iteratively to refine reciprocal square root approximations. The instruction operates on 128-bit SIMD registers, processing multiple 32-bit float elements in parallel. No integer flags are affected; floating-point exception flags may be set based on the results.

Pseudocode Operation

for i = 0 to 3
  Qd[i] ← (3.0 - (Qn[i] * Qm[i])) / 2.0

Example

VRSQRTS.F32 q0, q1, q2

Encoding

Binary Layout
1111001
0
0
D
1
sz
Vn
Vd
1111
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2200F10
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2200F10 VRSQRTS{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1111 | N | 0 | M | 1 | Vm
0xF2200F50 VRSQRTS{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1111 | N | 1 | M | 1 | Vm
0xEF200F10 VRSQRTS{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1111 | N | 0 | M | 1 | Vm
0xEF200F50 VRSQRTS{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1111 | N | 1 | M | 1 | Vm

Description

Vector Reciprocal Square Root Step multiplies the elements of one vector by the corresponding elements of another vector, subtracts each of the products from 3.0, divides these results by 2.0, and places the results into the elements of the destination vector. The operand and result elements are floating-point numbers. For details of the operation performed by this instruction see Floating-point reciprocal estimate and step. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            Elem[D[d+r],e,esize] = FPRSqrtStep(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize]);