fsub

Floating-Point Subtract (Half-Precision)

FSUB <Vd>.8H, <Vn>.8H, <Vm>.8H

Subtracts two half-precision floating-point vectors.

Details

Subtracts half-precision floating-point elements in Vm from corresponding elements in Vn, writing results to Vd. Operates on 8 half-precision (16-bit) floating-point values packed in 128-bit vectors. No condition flags are set by this instruction; floating-point exceptions are determined by FPCR settings. Requires FEAT_FP16 extension; AArch64-only.

Pseudocode Operation

for i = 0 to 7
  Vd[i*16 +: 16] ← FP16_Sub(Vn[i*16 +: 16], Vm[i*16 +: 16])

Example

FSUB v0.4s.8H, v1.4s.8H, v2.4s.8H

Encoding

Binary Layout
0
Q
0
01110
1
10
Rm
00
010
1
Rn
Rd
 
Format NEON FP16
Opcode 0x0EC01400
Extension FEAT_FP16 (NEON)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EC01400 FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 1 | 10 | Rm | 00 | 010 | 1 | Rn | Rd
0x0EA0D400 FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 011101 | sz | 1 | Rm | 11010 | 1 | Rn | Rd
0x1EE03800 FSUB <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 001 | 1 | 10 | Rn | Rd
0x1E203800 FSUB <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 1 | 10 | Rn | Rd
0x1E603800 FSUB <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 1 | 10 | Rn | Rd
0x65198000 FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 00 | 1 | 100 | Pg | 0000 | i1 | Zdn
0x65018000 FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 000 | 1 | 100 | Pg | Zm | Zdn
0x65000400 FSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 00 | 1 | Zn | Zd
0xC1A01C08 FSUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } A64 110000011 | sz | 1000000 | Rv | 111 | Zm | 00 | 1 | off3
0xC1A41C08 FSUB ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } A64 110000011 | 0 | 1001000 | Rv | 111 | Zm | 00 | 1 | off3
0xC1A11C08 FSUB ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } A64 110000011 | sz | 1000010 | Rv | 111 | Zm | 000 | 1 | off3
0xC1A51C08 FSUB ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } A64 110000011 | 0 | 1001010 | Rv | 111 | Zm | 000 | 1 | off3

Description

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];

bits(esize) element1;
bits(esize) element2;
bits(esize) diff;

bits(datasize) result;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    diff = FPSub(element1, element2, FPCR);
    Elem[result, e, esize] = if abs then FPAbs(diff, FPCR) else diff;

V[d, datasize] = result;