shll

Shift Left Long

SHLL <Vd>.<Td>, <Vn>.<Ts>, #<shift>

Shifts narrow vector left, extending to wide result.

Pseudocode Operation

for i = 0 to (128 >> (size+1)) - 1 do
  operand ← ZeroExtend(Vn[i], element_width)
  Vd[i] ← operand << imm
end for

Example

SHLL v0.4s.Td, v1.4s.Ts, #LSL

Encoding

Binary Layout

01110

28:24

size

23:22

10000

21:17

10011

16:12

11:10

9:5

4:0

Format SIMD Shift Imm

Opcode 0x2E213800

Extension NEON (SIMD)

Operands

Vd
Dest (Wide)
Vn
First source SIMD/FP vector register
shift
Imm

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2E213800	SHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #<shift>		A64		0 \| Q \| 1 \| 01110 \| size \| 10000 \| 10011 \| 10 \| Rn \| Rd

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. The SHLL instruction extracts vector elements from the lower half of the source register. The SHLL2 instruction extracts vector elements from the upper half of the source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = Vpart[n, part, datasize];
bits(2*datasize) result;
integer element;

for e = 0 to elements-1
    element = Int(Elem[operand, e, esize], unsigned) << shift;
    Elem[result, e, 2*esize] = element<2*esize-1:0>;

V[d, 2*datasize] = result;