vld4

Vector Load Multiple (4-Element Structure)

VLD4<c>.<size> <list>, [<Rn>]{!}

Loads four-element structures (e.g., RGBA) and de-interleaves them into four registers.

Pseudocode Operation

address ← Rn
for i = 0 to 7 do
  element_size_bits ← size_in_bits(size)
  Vd[i] ← [address + (i * element_size_bits / 8)]
  Vd+1[i] ← [address + (i * element_size_bits / 8) + (element_size_bits / 8)]
  Vd+2[i] ← [address + (i * element_size_bits / 8) + (2 * element_size_bits / 8)]
  Vd+3[i] ← [address + (i * element_size_bits / 8) + (3 * element_size_bits / 8)]
if (writeback) then
  Rn ← Rn + (4 * 8 * element_size_bits / 8)

Example

VLD4.size {r0-r3}, [r1]!

Encoding

Binary Layout
111101001
31:23
D
22
1
21
0
20
Rn
19:16
Vd
15:12
00
11:10
11
9:8
index_align
7:4
1101
3:0
 
Format NEON Load
Opcode 0xF4A0030D
Extension NEON (SIMD)

Operands

  • list
    Dest Registers
  • Rn
    First source / base general-purpose register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF4A0030F VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 11 | index_align | 1111
0xF4A0030D VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 11 | index_align | 1101
0xF4A00300 VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 11 | index_align | Rm
0xF4A0070F VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 11 | index_align | 1111
0xF4A0070D VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 11 | index_align | 1101
0xF4A00700 VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 11 | index_align | Rm
0xF4A00B0F VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 11 | index_align | 1111
0xF4A00B0D VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 11 | index_align | 1101
0xF4A00B00 VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 11 | index_align | Rm
0xF9A0030F VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 11 | index_align | 1111
0xF9A0030D VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 11 | index_align | 1101
0xF9A00300 VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 11 | index_align | Rm
0xF9A0070F VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 1 | 0 | Rn | Vd | 01 | 11 | index_align | 1111
0xF9A0070D VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 1 | 0 | Rn | Vd | 01 | 11 | index_align | 1101

Description

Load single 4-element structure to one lane of four registers loads one 4-element structure from memory into corresponding elements of four registers. Elements of the registers that are not loaded are unchanged. For details of the addressing mode, see Advanced SIMD addressing mode. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    CheckAdvSIMDEnabled();

    address = R[n];

    boolean nontemporal = FALSE;
    boolean tagchecked  = FALSE;
    AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked);
    if !IsAligned(address, alignment) then
        AArch32.Abort(address, AlignmentFault(accdesc));

    Elem[D[d], index,8*ebytes] = MemU[address,ebytes];
    Elem[D[d2],index,8*ebytes] = MemU[address+ebytes,ebytes];
    Elem[D[d3],index,8*ebytes] = MemU[address+2*ebytes,ebytes];
    Elem[D[d4],index,8*ebytes] = MemU[address+3*ebytes,ebytes];
    if wback then
        if register_index then
            R[n] = R[n] + R[m];
        else
            R[n] = R[n] + 4*ebytes;