frecpe

Vector Floating-Point Reciprocal Estimate

FRECPE <Vd>.<T>, <Vn>.<T>

Estimates reciprocal (1/x) for floats.

Details

Computes a floating-point reciprocal estimate (1/x approximation) for each element in the source vector and stores the result in the destination vector. Operates on 32-bit (sz=0) or 64-bit (sz=1) floating-point elements. The result is reduced-precision and intended for refinement via Newton-Raphson steps. No condition flags are affected. Available in AArch64 NEON.

Pseudocode Operation

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← FloatReciprocalEstimate(Vn[i])  // 32-bit float
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← FloatReciprocalEstimate(Vn[i])  // 64-bit float

Example

FRECPE v0.4s.T, v1.4s.T

Encoding

Binary Layout
0
Q
0
01110
1
111100
11101
10
Rn
Rd
 
Format SIMD Two Register
Opcode 0x0EF9D800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5EF9D800 FRECPE <Hd>, <Hn> A64 01 | 0 | 11110 | 1 | 111100 | 11101 | 10 | Rn | Rd
0x5EA1D800 FRECPE <V><d>, <V><n> A64 01 | 0 | 111101 | sz | 10000 | 11101 | 10 | Rn | Rd
0x0EF9D800 FRECPE <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 1 | 111100 | 11101 | 10 | Rn | Rd
0x0EA1D800 FRECPE <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 011101 | sz | 10000 | 11101 | 10 | Rn | Rd
0x650E3000 FRECPE <Zd>.<T>, <Zn>.<T> A64 01100101 | size | 00111 | 0 | 001100 | Zn | Zd

Description

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

if elements == 1 then
    CheckFPEnabled64();
else
    CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];

boolean merge = elements == 1 && IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);
bits(esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);

V[d, 128] = result;