fsqrt

Floating-Point Square Root (Half-Precision)

FSQRT <Vd>.8H, <Vn>.8H

Square root of half-precision vector.

Pseudocode Operation

for i = 0 to 7
  Vd.H[i] ← FP16_SquareRoot(Vn.H[i])
endfor

Example

FSQRT v0.4s.8H, v1.4s.8H

Encoding

Binary Layout
0
31
Q
30
1
29
01110
28:24
1
23
111100
22:17
11111
16:12
10
11:10
Rn
9:5
Rd
4:0
 
Format NEON FP16
Opcode 0x2EF9F800
Extension FEAT_FP16 (NEON)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Related

Other forms of fsqrt

  • fsqrt SVE Floating-Point Square Root
  • fsqrt Floating-Point Square Root (Scalar)
  • fsqrt Vector Floating-Point Square Root

Across architectures

Floating-Point Square Root : how x86, ARM, RISC-V, and PowerISA each do this.

More in FEAT_FP16 (NEON)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2EF9F800 FSQRT <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 1 | 111100 | 11111 | 10 | Rn | Rd
0x2EA1F800 FSQRT <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 011101 | sz | 10000 | 11111 | 10 | Rn | Rd
0x1EE1C000 FSQRT <Hd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 10000 | 11 | 10000 | Rn | Rd
0x1E21C000 FSQRT <Sd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 10000 | 11 | 10000 | Rn | Rd
0x1E61C000 FSQRT <Dd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 10000 | 11 | 10000 | Rn | Rd
0x650DA000 FSQRT <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 01100101 | size | 0011 | 0 | 1 | 101 | Pg | Zn | Zd

Description

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) result;
bits(esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = FPSqrt(element, FPCR);

V[d, datasize] = result;