fmul

Floating-point Multiply (Single)

FMUL <Sd>, <Sn>, <Sm>

Multiplies two single-precision floating-point registers.

Pseudocode Operation

operand1 ← Sn (32-bit float)
operand2 ← Sm (32-bit float)
result ← FPMul(operand1, operand2)
Sd ← result
UpdateFPSR(exception_flags)

Example

FMUL s0, s1, s2

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
Rm
20:16
0
15
00010
14:10
Rn
9:5
Rd
4:0
 
Format Float Data Proc
Opcode 0x1E200800
Extension F.P.

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sn
    First source 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register

Related

Other forms of fmul

  • fmul Floating-Point Multiply (Scalar)
  • fmul Vector Floating-Point Multiply
  • fmul SVE Floating-Point Multiply
  • fmul Floating-Point Multiply (Half-Precision)
  • fmul Floating-point Multiply (Double)

More in F.P.

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F009000 FMUL <Hd>, <Hn>, <Vm>.H[<index>] A64 01 | 0 | 11111 | 00 | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x5F809000 FMUL <V><d>, <V><n>, <Vm>.<Ts>[<index>] A64 01 | 0 | 111111 | sz | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x0F009000 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>] A64 0 | Q | 0 | 01111 | 00 | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x0F809000 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] A64 0 | Q | 0 | 011111 | sz | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x2E401C00 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 011 | 1 | Rn | Rd
0x2E20DC00 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11011 | 1 | Rn | Rd
0x1EE00800 FMUL <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 0 | 00010 | Rn | Rd
0x1E200800 FMUL <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0 | 00010 | Rn | Rd
0x1E600800 FMUL <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0 | 00010 | Rn | Rd
0x651A8000 FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 01 | 0 | 100 | Pg | 0000 | i1 | Zdn
0x65028000 FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 001 | 0 | 100 | Pg | Zm | Zdn
0x65000800 FMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 01 | 0 | Zn | Zd
0x64202000 FMUL <Zd>.H, <Zn>.H, <Zm>.H[<imm>] A64 01100100 | 0 | i3h | 1 | i3l | Zm | 0010 | 0 | 0 | Zn | Zd
0x64A02000 FMUL <Zd>.S, <Zn>.S, <Zm>.S[<imm>] A64 01100100 | 1 | 0 | 1 | i2 | Zm | 0010 | 0 | 0 | Zn | Zd

Description

Floating-point Multiply (scalar). This instruction multiplies the floating-point values of the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);

bits(esize) product = FPMul(operand1, operand2, FPCR);
Elem[result, 0, esize] = product;

V[d, 128] = result;