frint64x

Floating-Point Round to 64-bit Integer (Exact)

FRINT64X <Sd>, <Sn>

Rounds to 64-bit integer, exact exception.

Details

Rounds the source single-precision floating-point value to a 64-bit signed integer using the current rounding mode, and writes the result as a single-precision floating-point value to the destination. Signals an inexact exception if the input was not exactly representable as a 64-bit integer. Does not update the NZCV condition flags. Requires FEAT_FRINTTS extension; AArch64 only.

Pseudocode Operation

Xn_bits ← Sn
int64_val ← RoundUsingCurrentMode(FPUnpack(Xn_bits), 64)
if int64_val is inexact then signal_inexact_exception()
Sd ← FPPack(int64_val as single-precision floating-point)

Example

FRINT64X s0, s1

Encoding

Binary Layout
0
0
0
11110
00
10100
11
10000
Rn
Rd
 
Format Float Conversion
Opcode 0x1E29C000
Extension FEAT_FRINTTS

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sn
    First source 32-bit floating-point register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E21F800 FRINT64X <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 011100 | sz | 100001111 | 1 | 10 | Rn | Rd
0x1E29C000 FRINT64X <Sd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 10100 | 11 | 10000 | Rn | Rd
0x1E69C000 FRINT64X <Dd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 10100 | 11 | 10000 | Rn | Rd

Description

Floating-point Round to 64-bit Integer, using current rounding mode (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 64-bit integer size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When the result value is not numerically equal to the input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);
bits(esize) operand = V[n, esize];

Elem[result, 0, esize] = FPRoundIntN(operand, FPCR, rounding, intsize);

V[d, 128] = result;