fcmla
SVE Floating-Point Complex Multiply-Add
Performs complex multiply-accumulate.
Pseudocode Operation
for i = 0 to VL-1
if Pg[i] == '1' then
product ← FPComplexMultiply(Zn[i], Zm[i], rot)
Zda[i] ← FPAdd(Zda[i], product)
// else Zda[i] unchangedExample
Encoding
Operands
-
Zda
Accumulator scalable vector register (SVE) -
Pg
Mask -
Zn
First source scalable vector register (SVE) -
Zm
Second source scalable vector register (SVE) -
rot
Rot
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x2F001000 | FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate> | A64 | 0 | Q | 1 | 01111 | size | L | M | Rm | 0 | rot | 1 | H | 0 | Rn | Rd | ||
| 0x2E00C400 | FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate> | A64 | 0 | Q | 1 | 01110 | size | 0 | Rm | 110 | rot | 1 | Rn | Rd | ||
| 0x64000000 | FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const> | A64 | 01100100 | size | 0 | Zm | 0 | rot | Pg | Zn | Zda | ||
| 0x64A01000 | FCMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const> | A64 | 01100100 | 1 | 0 | 1 | i2 | Zm | 0001 | rot | Zn | Zda | ||
| 0x64E01000 | FCMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const> | A64 | 01100100 | 1 | 1 | 1 | i1 | Zm | 0001 | rot | Zn | Zda |
Description
Multiply the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the floating-point complex numbers in the first source vector by the corresponding complex number in the second source vector rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation. Then destructively add the products to the corresponding components of the complex numbers in the addend and destination vector, without intermediate rounding. These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element. Inactive elements in the destination vector register remain unmodified.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer pairs = VL DIV (2 * esize);
bits(PL) mask = P[g, PL];
bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) operand3 = Z[da, VL];
bits(VL) result;
for p = 0 to pairs-1
addend_r = Elem[operand3, 2 * p + 0, esize];
addend_i = Elem[operand3, 2 * p + 1, esize];
if ActivePredicateElement(mask, 2 * p + 0, esize) then
bits(esize) elt1_a = Elem[operand1, 2 * p + sel_a, esize];
bits(esize) elt2_a = Elem[operand2, 2 * p + sel_a, esize];
if neg_r then elt2_a = FPNeg(elt2_a, FPCR);
addend_r = FPMulAdd(addend_r, elt1_a, elt2_a, FPCR);
if ActivePredicateElement(mask, 2 * p + 1, esize) then
bits(esize) elt1_a = Elem[operand1, 2 * p + sel_a, esize];
bits(esize) elt2_b = Elem[operand2, 2 * p + sel_b, esize];
if neg_i then elt2_b = FPNeg(elt2_b, FPCR);
addend_i = FPMulAdd(addend_i, elt1_a, elt2_b, FPCR);
Elem[result, 2 * p + 0, esize] = addend_r;
Elem[result, 2 * p + 1, esize] = addend_i;
Z[da, VL] = result;