subs

Subtract and Set Flags (Extended)

SUBS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}}

Subtracts extended register and updates flags.

Pseudocode Operation

extended_Wm ← ExtendRegister(Wm, option); shifted_Wm ← extended_Wm << imm3; result ← Wn - shifted_Wm; Wd ← result; N ← result[31]; Z ← (result == 0); C ← BorrowFrom(Wn, shifted_Wm); V ← OverflowFrom(Wn, shifted_Wm, result)

Example

SUBS w0, Wn, w2

Encoding

Binary Layout

0

31

1

30

1

29

01011

28:24

00

23:22

1

21

Rm

20:16

option

15:13

imm3

12:10

Rn

9:5

Rd

4:0

 

Format Data Processing

Opcode 0x6B200000

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• Wm
  Second source / offset 32-bit integer register

Related

Other forms of subs

• subs Subtract and Set Flags (Immediate)
• subs Subtract and Set Flags (Shifted)
• subs Subtract and Return (A32)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x6B200000	SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}		A64		0 | 1 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0xEB200000	SUBS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}		A64		1 | 1 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0x71000000	SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}		A64		0 | 1 | 1 | 100010 | sh | imm12 | Rn | Rd
0xF1000000	SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}		A64		1 | 1 | 1 | 100010 | sh | imm12 | Rn | Rd
0x6B000000	SUBS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}		A64		0 | 1 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd
0xEB000000	SUBS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}		A64		1 | 1 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd

Description

Subtract (extended register), setting flags, subtracts a sign or zero-extended register value, followed by an optional left shift amount, from a register value, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result.

Operation

bits(datasize) result;
bits(datasize) operand1 = if n == 31 then SP[]<datasize-1:0> else X[n, datasize];
bits(datasize) operand2 = ExtendReg(m, extend_type, shift, datasize);
bits(4) nzcv;

operand2 = NOT(operand2);
(result, nzcv) = AddWithCarry(operand1, operand2, '1');

PSTATE.<N,Z,C,V> = nzcv;

X[d, datasize] = result;