fdiv

SVE Floating-Point Divide

FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Divides floating-point elements under predicate.

Details

Divides corresponding floating-point elements (Zdn by Zm), writing results back to Zdn under the control of predicate Pg in merging mode. The operation is performed element-by-element on 32-bit, 64-bit, or 16-bit (half-precision) floating-point values as indicated by the type specifier. No condition flags are affected; inactive elements are preserved in Zdn. Division by zero produces a signed infinity or NaN according to IEEE floating-point semantics. AArch64-only instruction requiring SVE extension.

Pseudocode Operation

for i ← 0 to VL/esize - 1
  if Pg[i] == 1 then
    Zdn[i] ← Zdn[i] / Zm[i]
  else
    Zdn[i] ← Zdn[i]  // unchanged

Example

FDIV z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
01100101
size
00
110
1
100
Pg
Zm
Zdn
 
Format SVE FP Binary
Opcode 0x650D8000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E403C00 FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 111 | 1 | Rn | Rd
0x2E20FC00 FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11111 | 1 | Rn | Rd
0x1EE01800 FDIV <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 0001 | 10 | Rn | Rd
0x1E201800 FDIV <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0001 | 10 | Rn | Rd
0x1E601800 FDIV <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0001 | 10 | Rn | Rd
0x650D8000 FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 110 | 1 | 100 | Pg | Zm | Zdn

Description

Divide active floating-point elements of the first source vector by corresponding floating-point elements of the second source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    bits(esize) element1 = Elem[operand1, e, esize];
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element2 = Elem[operand2, e, esize];
        Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
    else
        Elem[result, e, esize] = element1;

Z[dn, VL] = result;