frintx
Floating-Point Round to Integral (Exact)
FRINTX <Hd|Sd|Dd>, <Hn|Sn|Dn>
Rounds float to integral value using current mode, raising Inexact exception.
Details
Rounds the floating-point value in the source register to the nearest integer using the current rounding mode and raises an Inexact floating-point exception if the result differs from the input. The instruction does not set condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and always signals the Inexact exception condition when rounding occurs.
Pseudocode Operation
Vd ← RoundToIntegral(Vn); if Vd ≠ Vn then RaiseInexactException()Example
FRINTX Dd, Dn
Encoding
Binary Layout
0
0
0
11110
00
1001
110
10000
Rn
Rd
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x6506A000 | FRINTX <Zd>.<T>, <Pg>/M, <Zn>.<T> | A64 | 01100101 | size | 000 | 11 | 0 | 101 | Pg | Zn | Zd | ||
| 0x2E799800 | FRINTX <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 1 | 01110 | 0 | 1111001100 | 1 | 10 | Rn | Rd | ||
| 0x2E219800 | FRINTX <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 1 | 01110 | 0 | sz | 100001100 | 1 | 10 | Rn | Rd | ||
| 0x1EE74000 | FRINTX <Hd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 1001 | 110 | 10000 | Rn | Rd | ||
| 0x1E274000 | FRINTX <Sd>, <Sn> | A64 | 0 | 0 | 0 | 11110 | 00 | 1001 | 110 | 10000 | Rn | Rd | ||
| 0x1E674000 | FRINTX <Dd>, <Dn> | A64 | 0 | 0 | 0 | 11110 | 01 | 1001 | 110 | 10000 | Rn | Rd |
Description
Floating-point Round to Integral exact, using current rounding mode (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.
When the result value is not numerically equal to the input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPEnabled64(); boolean merge = IsMerging(FPCR); bits(128) result = if merge then V[d, 128] else Zeros(128); bits(esize) operand = V[n, esize]; Elem[result, 0, esize] = FPRoundInt(operand, FPCR, rounding, TRUE); V[d, 128] = result;