sdiv
SVE Signed Divide
SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
Divides signed integers.
Pseudocode Operation
for i = 0 to VL-1
if Pg[i] == '1' then
Zdn[i] ← Zdn[i] / Zm[i]
// else Zdn[i] unchanged
Example
SDIV z0.s.T, p0/m/M, z0.s.T, z2.s.T
Encoding
Binary Layout
00000100
31:24
size
23:22
0101
21:18
0
17
0
16
000
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
Operands
-
Zdn
Dest/Dividend -
Pg
Mask -
Zm
Divisor
Related
Other forms of sdiv
Across architectures
Integer Divide : how x86, ARM, RISC-V, and PowerISA each do this.
More in SVE
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x1AC00C00 | SDIV <Wd>, <Wn>, <Wm> | A64 | 0 | 0 | 0 | 11010110 | Rm | 00001 | 1 | Rn | Rd | ||
| 0x9AC00C00 | SDIV <Xd>, <Xn>, <Xm> | A64 | 1 | 0 | 0 | 11010110 | Rm | 00001 | 1 | Rn | Rd | ||
| 0x04140000 | SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 0101 | 0 | 0 | 000 | Pg | Zm | Zdn |
Description
Signed divide active elements of the first source vector by corresponding elements of the second source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;
for e = 0 to elements-1
integer element1 = Int(Elem[operand1, e, esize], unsigned);
if ActivePredicateElement(mask, e, esize) then
integer element2 = Int(Elem[operand2, e, esize], unsigned);
integer quotient;
if element2 == 0 then
quotient = 0;
else
quotient = RoundTowardsZero(Real(element1) / Real(element2));
Elem[result, e, esize] = quotient<esize-1:0>;
else
Elem[result, e, esize] = Elem[operand1, e, esize];
Z[dn, VL] = result;