scvtf

SVE Signed Integer Convert to Floating-Point

SCVTF <Zdn>.<T>, <Pg>/M, <Zdn>.<T>

Converts signed integers to floats.

Pseudocode Operation

for i = 0 to (VL/esize)-1
    if Pg[i]
        Zdn[i*esize+esize-1:i*esize] = ConvertSignedIntegerToFP(Zdn[i*esize+esize-1:i*esize])
    else
        Zdn[i*esize+esize-1:i*esize] = 0

Example

SCVTF z0.s.T, p0/m/M, z0.s.T

Encoding

Binary Layout
01100101
31:24
0
23
1
22
010
21:19
0
18
1
17
0
16
101
15:13
Pg
12:10
Zn
9:5
Zd
4:0
 
Format SVE Conversion
Opcode 0x6552A000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask

Related

Other forms of scvtf

  • scvtf Signed Integer Convert to Floating-Point
  • scvtf Signed Integer Convert to Floating-point

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F00E400 SCVTF <V><d>, <V><n>, #<fbits> A64 01 | 0 | 111110 | immh | immb | 11100 | 1 | Rn | Rd
0x0F00E400 SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits> A64 0 | Q | 0 | 011110 | immh | immb | 11100 | 1 | Rn | Rd
0x5E79D800 SCVTF <Hd>, <Hn> A64 01 | 0 | 11110 | 0 | 111100 | 11101 | 10 | Rn | Rd
0x5E21D800 SCVTF <V><d>, <V><n> A64 01 | 0 | 111100 | sz | 10000 | 11101 | 10 | Rn | Rd
0x0E79D800 SCVTF <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 0 | 111100 | 11101 | 10 | Rn | Rd
0x0E21D800 SCVTF <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 011100 | sz | 10000 | 11101 | 10 | Rn | Rd
0x1EC20000 SCVTF <Hd>, <Wn>, #<fbits> A64 0 | 0 | 0 | 11110 | 11 | 0 | 00 | 010 | scale | Rn | Rd
0x9EC20000 SCVTF <Hd>, <Xn>, #<fbits> A64 1 | 0 | 0 | 11110 | 11 | 0 | 00 | 010 | scale | Rn | Rd
0x1E020000 SCVTF <Sd>, <Wn>, #<fbits> A64 0 | 0 | 0 | 11110 | 00 | 0 | 00 | 010 | scale | Rn | Rd
0x9E020000 SCVTF <Sd>, <Xn>, #<fbits> A64 1 | 0 | 0 | 11110 | 00 | 0 | 00 | 010 | scale | Rn | Rd
0x1E420000 SCVTF <Dd>, <Wn>, #<fbits> A64 0 | 0 | 0 | 11110 | 01 | 0 | 00 | 010 | scale | Rn | Rd
0x9E420000 SCVTF <Dd>, <Xn>, #<fbits> A64 1 | 0 | 0 | 11110 | 01 | 0 | 00 | 010 | scale | Rn | Rd
0x1EE20000 SCVTF <Hd>, <Wn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 010 | 000000 | Rn | Rd
0x1E220000 SCVTF <Sd>, <Wn> A64 0 | 0 | 0 | 11110 | 00 | 1 | 00 | 010 | 000000 | Rn | Rd

Description

Convert to floating-point from the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        bits(d_esize) fpval = FixedToFP(element<s_esize-1:0>, 0, unsigned, FPCR, rounding, d_esize);
        Elem[result, e, esize] = ZeroExtend(fpval, esize);

Z[d, VL] = result;