fneg
SVE Floating-Point Negate
FNEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
Negates floats.
Pseudocode Operation
for i = 0 to VL-1
if Pg[i] == '1' then
Zdn[i] ← FPNegate(Zdn[i])
// else Zdn[i] unchanged
Example
FNEG z0.s.T, p0/m/M, z0.s.T
Encoding
Binary Layout
00000100
31:24
size
23:22
011
21:19
10
18:17
1
16
101
15:13
Pg
12:10
Zn
9:5
Zd
4:0
Operands
-
Zdn
Combined destination/source scalable vector register (SVE) -
Pg
Mask
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x2EF8F800 | FNEG <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 1 | 01110 | 1 | 111100 | 01111 | 10 | Rn | Rd | ||
| 0x2EA0F800 | FNEG <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 1 | 011101 | sz | 10000 | 01111 | 10 | Rn | Rd | ||
| 0x1EE14000 | FNEG <Hd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 10000 | 10 | 10000 | Rn | Rd | ||
| 0x1E214000 | FNEG <Sd>, <Sn> | A64 | 0 | 0 | 0 | 11110 | 00 | 10000 | 10 | 10000 | Rn | Rd | ||
| 0x1E614000 | FNEG <Dd>, <Dn> | A64 | 0 | 0 | 0 | 11110 | 01 | 10000 | 10 | 10000 | Rn | Rd | ||
| 0x041DA000 | FNEG <Zd>.<T>, <Pg>/M, <Zn>.<T> | A64 | 00000100 | size | 011 | 10 | 1 | 101 | Pg | Zn | Zd |
Description
Negate each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. This inverts the sign bit and cannot signal a floating-point exception. Inactive elements in the destination vector register remain unmodified.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
bits(esize) element = Elem[operand, e, esize];
Elem[result, e, esize] = FPNeg(element, FPCR);
Z[d, VL] = result;