fcvtzu
SVE Floating-Point Convert to Unsigned Integer
FCVTZU <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
Converts floats to unsigned integers (Truncate).
Details
SVE instruction that converts floating-point elements in a scalable vector to unsigned integer representation by truncation toward zero. Only active predicated elements are converted; inactive elements are zeroed. The instruction operates under predicate control with zeroing (/Z) semantics. This is an AArch64-only SVE instruction with no NZCV flag effects.
Pseudocode Operation
for i = 0 to (VL/esize)-1
if Pg[i]
Zdn[i*esize+esize-1:i*esize] = ConvertFPToUnsignedIntegerTruncate(Zdn[i*esize+esize-1:i*esize])
else
Zdn[i*esize+esize-1:i*esize] = 0Example
FCVTZU z0.s.T, p0/m/M, z0.s.T
Encoding
Binary Layout
01100101
0
1
011
0
1
1
101
Pg
Zn
Zd
Operands
-
Zdn
Combined destination/source scalable vector register (SVE) -
Pg
Mask
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x7F00FC00 | FCVTZU <V><d>, <V><n>, #<fbits> | A64 | 01 | 1 | 111110 | immh | immb | 11111 | 1 | Rn | Rd | ||
| 0x2F00FC00 | FCVTZU <Vd>.<T>, <Vn>.<T>, #<fbits> | A64 | 0 | Q | 1 | 011110 | immh | immb | 11111 | 1 | Rn | Rd | ||
| 0x7EF9B800 | FCVTZU <Hd>, <Hn> | A64 | 01 | 1 | 11110 | 1 | 1111001101 | 1 | 10 | Rn | Rd | ||
| 0x7EA1B800 | FCVTZU <V><d>, <V><n> | A64 | 01 | 1 | 11110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd | ||
| 0x2EF9B800 | FCVTZU <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 1 | 01110 | 1 | 1111001101 | 1 | 10 | Rn | Rd | ||
| 0x2EA1B800 | FCVTZU <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 1 | 01110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd | ||
| 0x1ED90000 | FCVTZU <Wd>, <Hn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 11 | 0 | 11 | 001 | scale | Rn | Rd | ||
| 0x9ED90000 | FCVTZU <Xd>, <Hn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 11 | 0 | 11 | 001 | scale | Rn | Rd | ||
| 0x1E190000 | FCVTZU <Wd>, <Sn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 00 | 0 | 11 | 001 | scale | Rn | Rd | ||
| 0x9E190000 | FCVTZU <Xd>, <Sn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 00 | 0 | 11 | 001 | scale | Rn | Rd | ||
| 0x1E590000 | FCVTZU <Wd>, <Dn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 01 | 0 | 11 | 001 | scale | Rn | Rd | ||
| 0x9E590000 | FCVTZU <Xd>, <Dn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 01 | 0 | 11 | 001 | scale | Rn | Rd | ||
| 0x1EF90000 | FCVTZU <Wd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 1 | 11 | 001 | 000000 | Rn | Rd | ||
| 0x9EF90000 | FCVTZU <Xd>, <Hn> | A64 | 1 | 0 | 0 | 11110 | 11 | 1 | 11 | 001 | 000000 | Rn | Rd |
Description
Convert to the unsigned integer nearer to zero from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.
If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
bits(esize) element = Elem[operand, e, esize];
bits(d_esize) res = FPToFixed(element<s_esize-1:0>, 0, unsigned, FPCR, rounding, d_esize);
Elem[result, e, esize] = Extend(res, esize, unsigned);
Z[d, VL] = result;