bsl

Bitwise Select

BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Selects bits from Vn or Vm based on Vd (mask). (Vd = (Vd & Vn) | (~Vd & Vm)).

Pseudocode Operation

for i = 0 to (datasize / 8) - 1
  Vd[i*8 +: 8] ← (Vd[i*8 +: 8] & Vn[i*8 +: 8]) | (~Vd[i*8 +: 8] & Vm[i*8 +: 8])

Example

BSL v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout

01110

28:24

23:22

20:16

00011

15:11

9:5

4:0

Format SIMD Three Register

Opcode 0x2E601C00

Extension NEON (SIMD)

Operands

Vd
Mask/Dest
Vn
First source SIMD/FP vector register
Vm
Second source SIMD/FP vector register

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2E601C00	BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 \| Q \| 1 \| 01110 \| 01 \| 1 \| Rm \| 00011 \| 1 \| Rn \| Rd
0x04203C00	BSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D		A64		00000100 \| 0 \| 0 \| 1 \| Zm \| 00111 \| 1 \| Zk \| Zdn

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1;
bits(datasize) operand3;
bits(datasize) operand4 = V[n, datasize];

operand1 = V[m, datasize];
operand3 = V[d, datasize];
V[d, datasize] = operand1 EOR ((operand1 EOR operand4) AND operand3);

bsl