msr

Move Register to Status Register

MSR<c> <spec_reg>_<fields>, <Rn>

Writes to CPSR or SPSR.

Pseudocode Operation

if R == 0 then
  dest ← CPSR
else
  dest ← SPSR
if c then dest[7:0] ← Rn[7:0]
if x then dest[15:8] ← Rn[15:8]
if s then dest[23:16] ← Rn[23:16]
if f then dest[31:24] ← Rn[31:24]
if R == 0 then
  CPSR ← dest
else
  SPSR ← dest

Example

MSR nzcv_fields, r1

Encoding

Binary Layout

cond

31:28

00010

27:23

mask

19:16

1111

15:12

0000

7:4

3:0

Format System

Opcode 0x0120F000

Extension A32 (System)

Operands

spec_reg
CPSR/SPSR
Rn
First source / base general-purpose register

Other forms of msr

msr Move to System Register
msr Move to Special Register (Banked)
msr Move Immediate to Special Register (A32)
msr Move Immediate to Special Register (Thumb)
msr Move Register to Special Register (Thumb)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x0120F200	MSR{<c>}{<q>} <banked_reg>, <Rn>	A32	cond \| 00010 \| R \| 1 \| 0 \| M1 \| 1111 \| 0 \| 0 \| 1 \| M \| 0000 \| Rn
0xF3808020	MSR{<c>}{<q>} <banked_reg>, <Rn>	T32	11110011100 \| R \| Rn \| 10 \| 0 \| 0 \| M1 \| 0 \| 0 \| 1 \| M \| 0 \| 0 \| 0 \| 0
0x0320F000	MSR{<c>}{<q>} <spec_reg>, #<imm>	A32	cond \| 00110 \| R \| 10 \| mask \| 1 \| 1 \| 1 \| 1 \| imm12
0x0120F000	MSR{<c>}{<q>} <spec_reg>, <Rn>	A32	cond \| 00010 \| R \| 1 \| 0 \| mask \| 1111 \| 0 \| 0 \| 0 \| 0 \| 0000 \| Rn
0xF3808000	MSR{<c>}{<q>} <spec_reg>, <Rn>	T32	11110011100 \| R \| Rn \| 10 \| 0 \| 0 \| mask \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0

Description

Move general-purpose register to Special register moves selected bits of a general-purpose register to the APSR, CPSR or SPSR_<current_mode>. Because of the Do-Not-Modify nature of its reserved bits, a read-modify-write sequence is normally required when the MSR instruction is being used at Application level and its destination is not APSR_nzcvq (CPSR_f). If an MSR (register) moves selected bits of an immediate value to the CPSR, the PE checks whether the value being written to PSTATE.M is legal. See Illegal changes to PSTATE.M. An MSR (register) executed in User mode: An MSR (register) executed in System mode is unpredictable if it attempts to update the SPSR. The CPSR.E bit is writable from any mode using an MSR instruction. Arm deprecates using this to change its value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    if write_spsr then
        if PSTATE.M IN {M32_User,M32_System} then
            UNPREDICTABLE;
        else
            SPSRWriteByInstr(R[n], mask);
    else
        // Attempts to change to an illegal mode will invoke the Illegal Execution state mechanism
        CPSRWriteByInstr(R[n], mask);

msr