lastb

SVE Extract Last Element Before

LASTB <Vd>.<T>, <Pg>, <Zn>.<T>

Extracts last active element (SIMD scalar destination).

Details

Extracts the last active element (as determined by the predicate) from a SVE vector and writes it to a SIMD scalar register; if no active elements exist, the destination register is unchanged. This instruction operates only in AArch64 state and does not modify the condition flags.

Pseudocode Operation

activecount ← CountActiveLanes(Pg, esize)
if activecount > 0 then
  Vd ← Zn[activecount - 1]
else
  Vd ← Vd

Example

LASTB v0.4s.T, p0/m, z1.s.T

Encoding

Binary Layout
00000101
size
10001
1
100
Pg
Zn
Vd
 
Format SVE Extract
Opcode 0x05238000
Extension SVE

Operands

  • Vd
    Dest Scalar
  • Pg
    Predicate
  • Zn
    Vector

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0521A000 LASTB <R><d>, <Pg>, <Zn>.<T> A64 00000101 | size | 10000 | 1 | 101 | Pg | Zn | Rd
0x05238000 LASTB <V><d>, <Pg>, <Zn>.<T> A64 00000101 | size | 10001 | 1 | 100 | Pg | Zn | Vd

Description

If there is an active element then extract the last active element from the final source vector register. If there are no active elements, extract the highest-numbered element. Then place the extracted element in the destination SIMD&FP register.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = Z[n, VL];
integer last = LastActiveElement(mask, esize);

if isBefore then
    if last < 0 then last = elements - 1;
else
    last = last + 1;
    if last >= elements then last = 0;
V[d, esize] = Elem[operand, last, esize];