swp

Swap Word

SWP <Ws>, <Wt>, [<Xn|SP>]

Atomic swap of a word.

Pseudocode Operation

address ← Xn; old_value ← [address]; [address] ← Ws; Wt ← old_value;

Example

SWP w6, w3, [x1]

Encoding

Binary Layout
10
31:30
111
29:27
0
26
00
25:24
0
23
0
22
1
21
Rs
20:16
1
15
000
14:12
00
11:10
Rn
9:5
Rt
4:0
 
Format Atomic
Opcode 0xB8208000
Extension LSE (Atomics)

Operands

  • Ws
    Shift amount 32-bit register
  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Related

Other forms of swp

  • swp Swap (A32)

More in LSE (Atomics)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xB8208000 SWP <Ws>, <Wt>, [<Xn|SP>] A64 10 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 1 | 000 | 00 | Rn | Rt
0xF8208000 SWP <Xs>, <Xt>, [<Xn|SP>] A64 11 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 1 | 000 | 00 | Rn | Rt

Description

Swap word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(datasize) data;
bits(datasize) store_value;
AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_SWP, acquire, release, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

store_value = X[s, datasize];

bits(datasize) comparevalue = bits(datasize) UNKNOWN;    // Irrelevant when not executing CAS
data = MemAtomic(address, comparevalue, store_value, accdesc);

X[t, regsize] = ZeroExtend(data, regsize);