rev

SVE Reverse Vector

REV <Zd>.<T>, <Zn>.<T>

Reverses the order of elements in the vector.

Pseudocode Operation

elements ← VL / esize
for i = 0 to elements - 1
  Zd[i] ← Zn[elements - 1 - i]

Example

REV z0.s.T, z1.s.T

Encoding

Binary Layout

00000101

31:24

size

23:22

111000001110

21:10

9:5

4:0

Format SVE Permute

Opcode 0x05383800

Extension SVE

Operands

Zd
Destination scalable vector register (SVE)
Zn
First source scalable vector register (SVE)

Other forms of rev

rev Reverse Bytes (Thumb), T32 (Thumb)
rev Reverse Bytes (64-bit), Base
rev Reverse Bytes (Thumb), A32 (Base)
rev Reverse Bytes (32-bit), Base
rev Reverse Bytes (A32), A32 (Base)

Across architectures

Byte Swap (Endianness Reversal) : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x5AC00800	REV <Wd>, <Wn>	A64	0 \| 1 \| 0 \| 11010110 \| 00000 \| 0000 \| 10 \| Rn \| Rd
0xDAC00C00	REV <Xd>, <Xn>	A64	1 \| 1 \| 0 \| 11010110 \| 00000 \| 0000 \| 11 \| Rn \| Rd
0x05344000	REV <Pd>.<T>, <Pn>.<T>	A64	00000101 \| size \| 110100010000 \| 0 \| Pn \| 0 \| Pd
0x05383800	REV <Zd>.<T>, <Zn>.<T>	A64	00000101 \| size \| 111000001110 \| Zn \| Zd

Description

Reverse the order of all elements in the source vector and place in the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
bits(VL) operand = Z[n, VL];
bits(VL) result = Reverse(operand, esize);
Z[d, VL] = result;

rev