ldaxrh

Load-Acquire Exclusive Register Halfword

LDAXRH <Wt>, [<Xn|SP>]

Loads a halfword with Acquire Exclusive semantics.

Details

Load-Acquire Exclusive Register Halfword loads a 16-bit halfword from memory with both Acquire and Exclusive semantics, establishing a one-way memory barrier and reserving the addressed location for exclusive write tracking. The instruction is AArch64-only, does not modify condition flags, and the loaded halfword is zero-extended to 32 bits. This instruction must be paired with a store exclusive to complete atomic halfword transactions.

Pseudocode Operation

Wt ← ZeroExtend(Mem16[Xn], 16)
ExclusiveMonitor[Xn] ← LOCKED
# Acquire semantics: subsequent memory operations appear after this load

Example

LDAXRH w3, [x1]

Encoding

Binary Layout
01
0010000
1
0
11111
1
11111
Rn
Rt
 
Format Load/Store Excl
Opcode 0x485FFC00
Extension Base (Atomic)

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x485FFC00 LDAXRH <Wt>, [<Xn|SP>{, #0}] A64 01 | 0010000 | 1 | 0 | 11111 | 1 | 11111 | Rn | Rt

Description

Load-Acquire Exclusive Register Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(16) data;

AccessDescriptor accdesc = CreateAccDescExLDST(MemOp_LOAD, TRUE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

// Tell the Exclusives monitors to record a sequence of one or more atomic
// memory reads from virtual address range [address, address+dbytes-1].
// The Exclusives monitor will only be set if all the reads are from the
// same dbytes-aligned physical address, to allow for the possibility of
// an atomicity break if the translation is changed between reads.
AArch64.SetExclusiveMonitors(address, 2);

data = Mem[address, 2, accdesc];
X[t, 32] = ZeroExtend(data, 32);