fcvtns

Floating-Point Convert to Signed Integer (Nearest, ties to Even)

FCVTNS <Wd|Xd>, <Hn|Sn|Dn>

Converts float to signed integer, rounding to nearest (bankers' round).

Pseudocode Operation

operand ← Vn
intval ← RoundTowardNearestEven(operand)
if intval > MaxInt(destination_width) or intval < MinInt(destination_width) then
  GenerateException(InvalidOperation)
else
  Rd ← SignExtend(intval)
  UpdateFlags(intval)
end

Example

FCVTNS Wd, Dn

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
00
20:19
000
18:16
000000
15:10
Rn
9:5
Rd
4:0
 
Format FP Conversion
Opcode 0x1E200000
Extension Floating Point

Operands

  • Wd|Xd
    Destination general-purpose register (32-bit/64-bit)
  • Hn|Sn|Dn
    First source SIMD&FP register (half, single or double-precision)

Related

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E79A800 FCVTNS <Hd>, <Hn> A64 01 | 0 | 11110 | 0 | 1111001101 | 0 | 10 | Rn | Rd
0x5E21A800 FCVTNS <V><d>, <V><n> A64 01 | 0 | 11110 | 0 | sz | 100001101 | 0 | 10 | Rn | Rd
0x0E79A800 FCVTNS <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 0 | 1111001101 | 0 | 10 | Rn | Rd
0x0E21A800 FCVTNS <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 0 | sz | 100001101 | 0 | 10 | Rn | Rd
0x1EE00000 FCVTNS <Wd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 000 | 000000 | Rn | Rd
0x9EE00000 FCVTNS <Xd>, <Hn> A64 1 | 0 | 0 | 11110 | 11 | 1 | 00 | 000 | 000000 | Rn | Rd
0x1E200000 FCVTNS <Wd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 1 | 00 | 000 | 000000 | Rn | Rd
0x9E200000 FCVTNS <Xd>, <Sn> A64 1 | 0 | 0 | 11110 | 00 | 1 | 00 | 000 | 000000 | Rn | Rd
0x1E600000 FCVTNS <Wd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 1 | 00 | 000 | 000000 | Rn | Rd
0x9E600000 FCVTNS <Xd>, <Dn> A64 1 | 0 | 0 | 11110 | 01 | 1 | 00 | 000 | 000000 | Rn | Rd

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to even (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round to Nearest rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(decode_fltsize) fltval;
bits(intsize) intval;

fltval = V[n, decode_fltsize];
intval = FPToFixed(fltval, 0, FALSE, FPCR, rounding, intsize);
X[d, intsize] = intval;