mvn.w

Move NOT (Wide)

MVN.W <Rd>, <Operand2>

Thumb-2 32-bit Move Inverse.

Details

Thumb-2 32-bit bitwise NOT: Rd ← NOT(Operand2). The second operand can be a register or a shifted register. If the S suffix is present, the condition flags N and Z are updated based on the result, and C is updated from the shifter carry-out; V is unaffected. Execution state: T32 only.

Pseudocode Operation

result ← NOT(Operand2)
Rd ← result
if S then
  N ← result[31]
  Z ← (result == 0)
  C ← shifter_carry_out

Example

MVN.W r0, r2

Encoding

Binary Layout

1110101

0011

1111

imm3

imm2

stype

Format Thumb2 Data Proc

Opcode 0xEA6F0000

Extension T32 (Thumb2)

Operands

Rd
Destination general-purpose register
Operand2
Flexible second operand (register or shifted register)

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x03E00000	MVN{<c>}{<q>} <Rd>, #<const>	A32	cond \| 00111 \| 11 \| 0 \| 0000 \| Rd \| imm12
0xF06F0000	MVN{<c>}{<q>} <Rd>, #<const>	T32	11110 \| i \| 0 \| 0011 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm8
0x01E00060	MVN{<c>}{<q>} <Rd>, <Rm>, RRX	A32	cond \| 00011 \| 11 \| 0 \| 0000 \| Rd \| 00000 \| 11 \| 0 \| Rm
0x01E00000	MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}	A32	cond \| 00011 \| 11 \| 0 \| 0000 \| Rd \| imm5 \| stype \| 0 \| Rm
0x43C0	MVN<c>{<q>} <Rd>, <Rm>	T32	010000 \| 1111 \| Rm \| Rd
0xEA6F0030	MVN{<c>}{<q>} <Rd>, <Rm>, RRX	T32	1110101 \| 0011 \| 0 \| 1111 \| 0 \| 000 \| Rd \| 00 \| 11 \| Rm
0xEA6F0000	MVN<c>.W <Rd>, <Rm>	T32	1110101 \| 0011 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm2 \| stype \| Rm
0x01E00010	MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>	A32	cond \| 00011 \| 11 \| 0 \| 0000 \| Rd \| Rs \| 0 \| stype \| 1 \| Rm

Description

Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. If the destination register is not the PC, the MVNS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = NOT(shifted);
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged