fsqrt

Floating-Point Square Root (Scalar)

FSQRT <Hd|Sd|Dd>, <Hn|Sn|Dn>

Calculates square root.

Pseudocode Operation

if HaveFPExt() then
  Vd ← FPSqrt(Vn)
else
  UNDEFINED

Example

FSQRT Dd, Dn

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
10000
21:17
11
16:15
10000
14:10
Rn
9:5
Rd
4:0
 
Format FP Data Processing
Opcode 0x1E21C000
Extension Floating Point

Operands

  • Hd|Sd|Dd
    Destination SIMD&FP register (half, single or double-precision)
  • Hn|Sn|Dn
    First source SIMD&FP register (half, single or double-precision)

Related

Other forms of fsqrt

  • fsqrt SVE Floating-Point Square Root
  • fsqrt Vector Floating-Point Square Root
  • fsqrt Floating-Point Square Root (Half-Precision)

Across architectures

Floating-Point Square Root : how x86, ARM, RISC-V, and PowerISA each do this.

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2EF9F800 FSQRT <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 1 | 111100 | 11111 | 10 | Rn | Rd
0x2EA1F800 FSQRT <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 011101 | sz | 10000 | 11111 | 10 | Rn | Rd
0x1EE1C000 FSQRT <Hd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 10000 | 11 | 10000 | Rn | Rd
0x1E21C000 FSQRT <Sd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 10000 | 11 | 10000 | Rn | Rd
0x1E61C000 FSQRT <Dd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 10000 | 11 | 10000 | Rn | Rd
0x650DA000 FSQRT <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 01100101 | size | 0011 | 0 | 1 | 101 | Pg | Zn | Zd

Description

Floating-point Square Root (scalar). This instruction calculates the square root of the value in the SIMD&FP source register and writes the result to the SIMD&FP destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else 0<127:0>;

bits(esize) operand = V[n, esize];

Elem[result, 0, esize] = FPSqrt(operand, FPCR);

V[d, 128] = result;