sri
Shift Right and Insert
Shifts source right and inserts into destination.
Pseudocode Operation
for i = 0 to elements-1 do
shifted ← Vn[i] >> shift
Vd[i] ← (Vd[i] & ~mask) | (shifted & mask)
endfor
where mask selects the lower (element_width - shift) bits
Example
Encoding
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
shift
Imm
Related
More in NEON (SIMD)
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x7F404400 | SRI D<d>, D<n>, #<shift> | A64 | 01 | 1 | 111110 | immh | immb | 01000 | 1 | Rn | Rd | ||
| 0x2F004400 | SRI <Vd>.<T>, <Vn>.<T>, #<shift> | A64 | 0 | Q | 1 | 011110 | immh | immb | 01000 | 1 | Rn | Rd | ||
| 0x4500F000 | SRI <Zd>.<T>, <Zn>.<T>, #<const> | A64 | 01000101 | tszh | 0 | tszl | imm3 | 11110 | 0 | Zn | Zd |
Description
Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) operand2 = V[d, datasize];
bits(datasize) result;
bits(esize) mask = LSR(Ones(esize), shift);
bits(esize) shifted;
for e = 0 to elements-1
shifted = LSR(Elem[operand, e, esize], shift);
Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
V[d, datasize] = result;