mls

Multiply Subtract (A32)

MLS<c> <Rd>, <Rn>, <Rm>, <Ra>

Calculates Rd = Ra - (Rn * Rm).

Details

Multiply Subtract multiplies Rn and Rm, subtracts the product from Ra, and stores the 32-bit result in Rd. The N and Z flags are updated based on the result; the C and V flags are unpredictable. This is an A32 instruction (ARMv6T2 and later) available in all privilege levels.

Pseudocode Operation

product ← Rn * Rm
Rd ← Ra - product
N ← Rd[31]
Z ← (Rd == 0)
C ← unpredictable
V ← unpredictable

Example

MLS r0, r1, r2, r5

Encoding

Binary Layout
cond
0000
011
0
Rd
Ra
Rm
1001
Rn
 
Format Multiply
Opcode 0x00600090
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register
  • Ra
    Minuend

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x00600090 MLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> A32 cond | 0000 | 011 | 0 | Rd | Ra | Rm | 1001 | Rn
0xFB000010 MLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> T32 111110110 | 000 | Rn | Ra | Rd | 00 | 01 | Rm

Description

Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand1 = SInt(R[n]);  // operand1 = UInt(R[n]) produces the same final results
    operand2 = SInt(R[m]);  // operand2 = UInt(R[m]) produces the same final results
    addend   = SInt(R[a]);  // addend   = UInt(R[a]) produces the same final results
    result = addend - operand1 * operand2;
    R[d] = result<31:0>;