ldrb.w

Load Register Byte (Wide)

LDRB.W <Rt>, [<Rn>, #<imm>]

Thumb-2 32-bit Load Byte.

Details

Load an 8-bit byte from memory at address [Rn + imm12] into Rt, zero-extending to 32 bits. The immediate offset is unsigned and ranges from 0 to 4095 bytes. Condition flags (N, Z, C, V) are not affected. T32 (Thumb-2) instruction only.

Pseudocode Operation

address ← Rn + ZeroExtend(imm12, 32);
Rt ← ZeroExtend([address]<7:0>, 32);

Example

LDRB.W r3, [r1, #16]

Encoding

Binary Layout
111110001
00
1
Rn
Rt
imm12
 
Format Thumb Load
Opcode 0xF8900000
Extension T32 (Thumb2)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x05500000 LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}] A32 cond | 010 | 1 | U | 1 | 0 | 1 | Rn | Rt | imm12
0x04500000 LDRB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> A32 cond | 010 | 0 | U | 1 | 0 | 1 | Rn | Rt | imm12
0x05700000 LDRB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! A32 cond | 010 | 1 | U | 1 | 1 | 1 | Rn | Rt | imm12
0x7800 LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] T32 011 | 1 | 1 | imm5 | Rn | Rt
0xF8900000 LDRB{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}] T32 111110001 | 00 | 1 | Rn | Rt | imm12
0xF8100C00 LDRB{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}] T32 111110000 | 00 | 1 | Rn | Rt | 1 | 1 | 0 | 0 | imm8
0xF8100900 LDRB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> T32 111110000 | 00 | 1 | Rn | Rt | 1 | 0 | U | 1 | imm8
0xF8100D00 LDRB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! T32 111110000 | 00 | 1 | Rn | Rt | 1 | 1 | U | 1 | imm8
0x045F0000 LDRB{<c>}{<q>} <Rt>, <label> A32 cond | 010 | P | U | 1 | W | 1 | 1111 | Rt | imm12
0xF81F0000 LDRB{<c>}{<q>} <Rt>, <label> T32 11111000 | U | 00 | 1 | 1111 | Rt | imm12
0x07500000 LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] A32 cond | 011 | 1 | U | 1 | 0 | 1 | Rn | Rt | imm5 | stype | 0 | Rm
0x06500000 LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} A32 cond | 011 | 0 | U | 1 | 0 | 1 | Rn | Rt | imm5 | stype | 0 | Rm
0x07700000 LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! A32 cond | 011 | 1 | U | 1 | 1 | 1 | Rn | Rt | imm5 | stype | 0 | Rm
0x5C00 LDRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] T32 0101 | 1 | 1 | 0 | Rm | Rn | Rt

Description

Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

Operation

if CurrentInstrSet() == InstrSet_A32 then
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        R[t] = ZeroExtend(MemU[address,1], 32);
        if wback then R[n] = offset_addr;
else
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        R[t] = ZeroExtend(MemU[address,1], 32);
        if wback then R[n] = offset_addr;